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October 17, 2006 © Cypress Semiconductor Corp. 2004-2006 — Document No. 38-12028 Rev. *F 1PSoC® Mixed-Signal Array Final Data SheetCY8C24123A, CY8C24223A, and CY8C24423APSoC® Functional OverviewThe PSoC® family consists of many Mixed-Signal Array withOn-Chip Controller devices. These devices are designed toreplace multiple traditional MCU-based system componentswith one, low cost single-chip programmable device. PSoCdevices include configurable blocks of analog and digital logic,as well as programmable interconnects. This architectureallows the user to create customized peripheral configurationsthat match the requirements of each individual application.Additionally, a fast CPU, Flash program memory, SRAM datamemory, and configurable IO are included in a range of conve-nient pinouts and packages.The PSoC architecture, as illustrated on the left, is comprised offour main areas: PSoC Core, Digital System, Analog System,and System Resources. Configurable global busing allows allthe device resources to be combined into a complete customsystem. The PSoC CY8C24x23A family can have up to three IOports that connect to the global digital and analog interconnects,providing access to 4 digital blocks and 6 analog blocks.The PSoC CoreThe PSoC Core is a powerful engine that supports a rich fea-ture set. The core includes a CPU, memory, clocks, and config-urable GPIO (General Purpose IO).The M8C CPU core is a powerful processor with speeds up to24 MHz, providing a four MIPS 8-bit Harvard architecture micro-Features■ Powerful Harvard Architecture Processor❐ M8C Processor Speeds to 24 MHz❐ 8x8 Multiply, 32-Bit Accumulate❐ Low Power at High Speed❐ 2.4 to 5.25V Operating Voltage❐ Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP)❐ Industrial Temperature Range: -40°C to +85°C■ Advanced Peripherals (PSoC Blocks)❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:- Up to 14-Bit ADCs- Up to 9-Bit DACs- Programmable Gain Amplifiers- Programmable Filters and Comparators❐ 4 Digital PSoC Blocks Provide:- 8- to 32-Bit Timers, Counters, and PWMs- CRC and PRS Modules- Full-Duplex UART- Multiple SPI™ Masters or Slaves- Connectable to all GPIO Pins❐ Complex Peripherals by Combining Blocks■ Precision, Programmable Clocking❐ Internal ±2.5% 24/48 MHz Oscillator❐ High-Accuracy 24 MHz with Optional 32 kHz Crystal and PLL❐ Optional External Oscillator, up to 24 MHz❐ Internal Oscillator for Watchdog and Sleep■ Flexible On-Chip Memory❐ 4K Flash Program Storage 50,000 Erase/Write Cycles❐ 256 Bytes SRAM Data Storage❐ In-System Serial Programming (ISSP)❐ Partial Flash Updates❐ Flexible Protection Modes❐ EEPROM Emulation in Flash■ Programmable Pin Configurations❐ 25 mA Sink on all GPIO❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO❐ Up to 10 Analog Inputs on GPIO❐ Two 30 mA Analog Outputs on GPIO❐ Configurable Interrupt on all GPIO■ New CY8C24x23A PSoC Device❐ Derived from the CY8C24x23 Device❐ Low Power and Low Voltage (2.4V)■ Additional System Resources❐ I2C™ Slave, Master, and Multi-Master to 400 kHz❐ Watchdog and Sleep Timers❐ User-Configurable Low Voltage Detection❐ Integrated Supervisory Circuit❐ On-Chip Precision Voltage Reference ■ Complete Development Tools❐ Free Development Software (PSoC Designer™)❐ Full-Featured, In-Circuit Emulator and Programmer❐ Full Speed Emulation❐ Complex Breakpoint Structure❐ 128K Trace MemoryDIGITAL SYSTEMSRAM256 BytesInterruptControllerSleep and WatchdogMultiple Clock Sources(Includes IMO, ILO, PLL, and ECO)Global Digital InterconnectGlobal Analog InterconnectPSoC CORECPU Core (M8C)SROM Flash 4KDigitalBlock ArrayMultiply Accum.Switch Mode PumpInternal Voltage Ref.DigitalClocksPOR and LVDSystem ResetsDecimatorSYSTEM RESOURCESANALOG SYSTEMAnalog RefAnalog Input MuxingI2CPort 2 Port 1 Port 0Analog DriversSystem BusAnalog Block Array[+] Feedback October 17, 2006 Document No. 38-12028 Rev. *F 2CY8C24x23A Final Data Sheet PSoC® Overviewprocessor. The CPU utilizes an interrupt controller with 11 vec-tors, to simplify programming of real time embedded events.Program execution is timed and protected using the includedSleep and Watchdog Timers (WDT).Memory encompasses 4 KB of Flash for program storage, 256bytes of SRAM for data storage, and up to 2 KB of EEPROMemulated using the Flash. Program Flash utilizes four protec-tion levels on blocks of 64 bytes, allowing customized softwareIP protection.The PSoC device incorporates flexible internal clock genera-tors, including a 24 MHz IMO (internal main oscillator) accurateto 2.5% over temperature and voltage. The 24 MHz IMO canalso be doubled to 48 MHz for use by the digital system. A lowpower 32 kHz ILO (internal low speed oscillator) is provided forthe Sleep timer and WDT. If crystal accuracy is desired, theECO (32.768 kHz external crystal oscillator) is available for useas a Real Time Clock (RTC) and can optionally generate a crys-tal-accurate 24 MHz system clock using a PLL. The clocks,together with programmable clock dividers (as a SystemResource), provide the flexibility to integrate almost any timingrequirement into the PSoC device.PSoC GPIOs provide connection to the CPU, digital and analogresources of the device. Each pin’s drive mode may be selectedfrom eight options, allowing great flexibility in external interfac-ing. Every pin also has the capability to generate a system inter-rupt on high level, low level, and change from last read. The Digital SystemThe Digital System is composed of 4 digital PSoC blocks. Eachblock is an 8-bit resource that can be used alone or combinedwith other blocks to form 8, 16, 24, and 32-bit peripherals, whichare called user module references. Digital System Block DiagramDigital peripheral configurations include those listed below.■ PWMs (8 to 32 bit)■ PWMs with Dead band (8 to 24 bit)■ Counters (8 to 32 bit)■ Timers (8 to 32 bit)■ UART 8 bit with selectable parity■ SPI master and slave■ I2C slave and multi-master (1 available as a System Resource)■ Cyclical Redundancy Checker/Generator (8 to 32 bit)■ IrDA■ Pseudo Random Sequence Generators (8 to 32 bit)The digital blocks can be connected to any GPIO through aseries of global buses that can route any signal to any pin. Thebuses also allow for signal multiplexing and for performing logicoperations. This configurability frees your designs from the con-straints of a fixed peripheral controller.Digital blocks are provided in rows of four, where the number ofblocks varies by PSoC device family. This allows you the opti-mum choice of system resources for your application. Familyresources are shown in the table titled “PSoC Device Charac-teristics” on page 3.The Analog SystemThe Analog System is composed of 6 configurable blocks, eachcomprised of an opamp circuit allowing the creation of complexanalog signal flows. Analog peripherals are very flexible andcan be customized to support specific application requirements.Some of the more common PSoC analog functions (most avail-able as user modules) are listed below.■ Analog-to-digital converters (up to 2, with 6- to 14-bit resolu-tion, selectable as Incremental, Delta Sigma, and SAR)■ Filters (2 and 4 pole band-pass, low-pass, and notch)■ Amplifiers (up to 2, with selectable gain to 48x)■ Instrumentation amplifiers (1 with selectable gain to 93x)■ Comparators (up to 2, with 16 selectable thresholds) ■ DACs (up to 2, with 6- to 9-bit resolution)■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)■ High current output drivers (two with 30 mA drive as a PSoC Core resource)■ 1.3V reference (as a System Resource)■ DTMF Dialer■ Modulators■ Correlators■ Peak Detectors■ Many other topologies possibleDIGITAL SYSTEMTo System BusDigital Clocks From CoreDigital PSoC Block ArrayTo Analog System8Row InputConfiguration Row Output Configuration888 Row 0DBB00 DBB01 DCB02 DCB0344GIE[7:0]GIO[7:0]GOE[7:0]GOO[7:0]Global Digital InterconnectPort 2Port 1Port 0[+] Feedback
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